The present invention relates to a display device having an active-matrix display panel containing a vertical scanning circuit and a horizontal scanning circuit, and also having a timing generator and the like that supplies controlling timing signals to the display panel. More particularly, the invention relates to an improvement in making adjustments to the linearity, the center position, and the like, of a picture on the display panel.
A brief explanation will now be given of an example of a display device with reference to FIG. 10. The display panel for the display device has a plurality of gate lines X arranged in the form of rows, a plurality of signal lines Y arranged in the form of columns, and a plurality of pixels PXL each arranged at the intersection between each gate line X and each signal line Y. The pixels PXL are formed of, for example, minuscule liquid crystal cells that are arranged in the form of a matrix to form a picture. Switching devices, such as thin film transistors Tr or the like, are integrated to drive the individual pixels PXL. Further, the display panel includes a vertical scanning circuit 101 that sequentially scans the respective gate lines X in the vertical direction in accordance with timing signals, such as vertical start signals VST and a vertical clock signal VCK and the like, so as to select the pixels PXL for one line at every one horizontal period. One vertical scanning operation is completed for one vertical scanning period. The display panel also has a horizontal scanning circuit 102 that sequentially scans the respective signal lines Y within one horizontal period in accordance with horizontal start signals HST and a horizontal clock signal HCK so as to sample a video signal Vsig supplied from a video line 103 and to write the sampled signal points into the selected pixels PXL for one line. More specifically, each signal line Y is connected to the video line 103 via a horizontal switch HSW so as to receive the video signal Vsig from the exterior. The horizontal scanning circuit 102, which is formed of a shift register, sequentially transmits the horizontal start signals HST based on the horizontal clock signal HCK so that it sequentially outputs sampling pulses to cause the respective horizontal switches HSW to sequentially open or close, thereby sampling the video signal Vsig onto the respective signal lines Y.
FIG. 11 is a schematic block diagram illustrating the construction of a display device by the application of the display panel shown in FIG. 10 to a display. A timing generator 105 is connected to a display panel 104 and supplies the above-described various types of timing signals HCK, HST, VCK, VST to the display panel 104. The display panel 104 is operated in response to the timing signals and sequentially provides video signals Vsig to the pixels, whereby a desired image can be displayed. There are a variety of standards for video signals that are input from the exterior. For example, there are about 100 types of various formats of VGA signals when the display panel is applied to a computer data display system or the like. However, the display panel 104 of this display device is operable only with the single or the limited few types of synchronizing signals. Video signals having different synchronizing signals from predetermined timing signals have their timings converted via a scan converter 106 and are then supplied to the display panel 104. For performing this conversion, a field memory 107 is provided for the display device. The writing timing and reading timing of the video signals into/from the field memory 107 are suitably adjusted so as to match the driving timing inherent in the display panel 104. This necessitates ICs for the scan converter 106 and ICs for the field memory 107, thus increasing costs of the display system.